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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Output Driver Impedance
HSUL_12 Driver Output Timing Reference Load
The timing reference loads are not intended as a precise representation of any particu-
lar system environment or a depiction of the actual load presented by a production test-
er. System designers should use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers correlate to their production
test conditions, generally with one or more coaxial transmission lines terminated at the
tester electronics.
Figure 92: HSUL_12 Driver Output Reference Load for Timing and Slew Rate
LPDDR2
V REF
0.5 × V DDQ
50
Output
C LOAD = 5pF
V TT = 0.5 × V DDQ
Note:
1. All output timing parameter values ( t DQSCK, t DQSQ, t QHS, t HZ, t RPRE etc.) are reported
with respect to this reference load. This reference load is also used to report slew rate.
Output Driver Impedance
Output driver impedance is selected by a mode register during initialization. To achieve
tighter tolerances, ZQ calibration is required. Output specifications refer to the default
output drive unless specifically stated otherwise. The output driver impedance R ON is
defined by the value of the external reference resistor R ZQ as follows:
R ONPU = V DDQ - V OUT
ABS(I OUT )
When R ONPD is turned off.
R ONPD =
V OUT
ABS(I OUT )
When R ONPU is turned off.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
131
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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